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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
INTRODUCTION
64-LQFP-1010 S5L9276 is a single chip ISO/IEC 11172-3 Layer III audio decoder, capable of decoding compressed elementary bit stream as specified in ISO/IEC standard. As a decoder for the DISC-MAN, it can provide you more small and cheaper solution for MP3 player application. S5L9276 is low voltage IC that can read MP3 and CD-ROM format discs and can be applied to various products.
FEATURES
* * * * * * * * * * * * * * * * * * * * * * * Includes CD-ROM decoder with ECC and EDC ISO/IEC 11172-3 L1/L2/L3 Decoding. ISO/IEC 13818-3 L1/L2/L3 Decoding Supports All MPEG Bit Rates including free format for ISO/IEC 11172-3. Supports All MPEG Bit Rates except 8kbps and free format for ISO/IEC 13818-3. Supports 32/44.1/48kHz Spl for ISO/IEC 11172-3. (For variable bit rate, support only 44.1kHz sampling rate.) Supports 32/44.1/48kHz and 16/22.05/24 kHz for ISO/IEC 13818-3. (For variable bit rate, support only 44.1KHz & 22.05kHz sampling rate.) Single/ Dual/ Stereo// Joint Stereo Supports Any Combination of Intensity Stereo & MS Stereo Serial Host Interface Supports Off-chip DAC Anti Shock Memory Controller Supports 16Mbit EDO/FP DRAM Use of Standard Crystal 16.9344MHz 16.9344MHz Clock Output Port Power Save Mode : POWER-DOWN, SLEEP, POWER_SAVE Pause and Replay Fast Forward Fast Backward (Rewind) Back Skip Forward Skip CDFS(CD-ROM File System) Decoding (ISO9660, Joliet, and Romeo Format) Low Power Dissipation : 65mA @3.0 volts
ORDERING INFORMATION
Device S5L9276X01 Package 64-LQFP-1010 Supply Voltage 2.7V 3.3V Operating Temperature -20C +75C
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
FUNCTIONAL BLOCK DIAGRAM
CD-MP3 Decoder Chip
CD-ROM Decoder
DSP
DAC I/F
Memory Management Unit Host Interface
ckgUnit
DRAM Controller
4M x 4 bits DRAM
Host MCU
Figure 1. Functional Block Diagram of S5L9276
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
APPLICATION DIAGRAM
40pF 2 16.9344MHz 40pF 3 1K 4 5 XOUT CLK XO XI
820pF 10 FILTER0 GND 940pF 14 FILTER1
Test Pin Connection
40
SCAN_EN
41 TEST2 42 TEST1 43 TEST0 GND
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
DRAM Connection
S5L9276 DA11 DA0 - 10 DDAT0 - 3 RASB CASB OEB WEB
16Mbit(4M x 4 bit) DRAM 3.3V, 60ns, 2K refresh KM44V4100C (FP) KM44V4104C (EDO)
A0 - 10 DQ0 - 3 RAS CAS 1M 1M 1M 1M 1M OE W VDD VDD VDD
Figure 2. Interface with 4Mx4bit DRAM Type A (2K ref. Product)
16Mbit(4M x 4 bit) DRAM 3.3V, 60ns, 4K refresh S5L9276 DA0 - 11 DDAT0 - 3 RASB CASB OEB WEB A0 - 11 DQ0 - 3 RAS CAS 1M OE W VDD VDD VDD
Figure 3. Interface with 4Mx4bit DRAM Type B (4K ref. Product) ETC SP_SEL (pin15) = GND AD1(pin34) = OPEN AD2(pin29) = OPEN AD3(pin28) = OPEN DAII(pin30) = GND
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
PIN CONFIGURATION
DDAT3
DDAT2 50
CASB
DA03
DA02
DA01
DA00
DA09
DA04
DA05
DA06
DA07
DA08
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD XI XO XOUT CLK RESETB PLL0 VDDA PLL0 VSSA PLL0 VBBA FILTER_0 PLL1 VDDA PLL1 VSSA PLL1 VBBA FILTER_1 SP_SEL VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16
49 48 47 46 45 44 43 42
VDD
VSS
OEB
VSS RASB WEB DDAT1 DDAT0 TEST0 TEST1 TEST2 SCAN_EN MINT MDOUT MLAT MCK MDAT_AD0 AD1 VDD
S5L9276X
41 40 39 38 37 36 35 34 33
ADAT
ACLK
DA11
DA10
ACLK EXT
CD DATA
CD BCK
BCLK
VDD
CDP CLK
CD LRCK
Figure 4. 64 pin Low profile Quad Flat Package (LQFP)
CD C2PO
LRCK
VSS
AD3
AD2
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VDD XI XO XOUT CLK RESETB PLL0 VDDA PLL0 VSSA PLL0 VBBA FILTER_0 PLL1 VDDA PLL1 VSSA PLL1 VBBA FILTER_1 SP_SEL VSS VDD ACLK EXT CD CLK CD DATA CD LRCK CD BCK CD C2PO ACLK BCLK LRCK ADAT AD3 AD2 DA11 DA10 VSS I/O P I O O I I P G G O P G G O I G P I O I I I I O O O O I/O I/O O O G Digital Power X'tal Oscillator input(16.9344MHz) X'tal Oscillator output Buffered Output of XO System Clock input System Reset Active LOW Analog Power for PLL0 Analog Ground for PLL0 Analog Ground for PLL0 External Capacitor port for PLL0 Analog Power for PLL1 Analog Ground for PLL1 Analog Ground for PLL1 External Capacitor port for PLL0 Tied to GROUND. Digital Ground Digital Power External Audio Clock source Clock Output for CD DSP IC Data from CD DSP IC LRCK from CD DSP IC BCK from CD DSP IC C2PO from CD DSP IC Audio clock to DAC clock input BCLK to DAC LRCK to DAC Data to DAC Open (Not Used) Open (Not Used) Address Output 11 for DRAM Address Output 10 for DRAM Digital Ground Description
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
PIN DESCRIPTION (Continued)
Pin No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol VDD AD1 MDAT_AD0 MCK MLAT MDOUT MINT SCAN_EN TEST2 TEST1 TEST0 DDAT0 DDAT1 WEB RASB VSS VDD DDAT2 DDAT3 CASB DA08 DA07 DA06 DA05 DA04 DA09 DA00 DA01 DA02 DA03 OEB VSS I/O P I/O I I I O O I I I I B B O O G P B B O O O O O O O O O O O O G Digital Power Open (Not Used) Data input pin Micom Clock pin Data Latch input pin Data from CD-MP3 to MCU Interrupt output to MCU Scan Test enable Tied to GROUND. Tied to GROUND. Tied to GROUND. Data0 BUS for External DRAM Data1 BUS for External DRAM Write Enable for External DRAM Row Address for External DRAM Digital Ground Digital Power Data2 BUS for External DRAM Data3 BUS for External DRAM Column Address for External DRAM Address Output8 for DRAM Address Output7 for DRAM Address Output6 for DRAM Address Output5 for DRAM Address Output4 for DRAM Address Output9 for DRAM Address Output0 for DRAM Address Output1 for DRAM Address Output2 for DRAM Address Output3 for DRAM Output to make data output to " Hi-Z" at DRAM Digital Ground Description
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
ABSOLUTE MAXIMUM RATINGS
Parameter power supply voltage Input supply voltage Symbol VDD VI 3.3V I/O 5V-tolerant Operating temperature Storage temperature TOPR TSTG -20 70 -40 125 Rating -0.3 + 3.8 -0.3 VDD + 0.3 -0.3 5.5 C C Unit V V
ELECTRICAL CHARACTERISTICS
Pin Number Pin 10, Pin14 Pin2:Pin3 Pin4,Pin19,Pin39,Pin28,Pin29 Pin6,Pin20,Pin21,Pin22,Pin23,Pin36,Pin37 Pin5,Pin18,Pin40,in41,Pin42,Pin43 Pin28,Pin29,Pin34,Pin35,Pin44,Pin45,Pin50,Pin51 Pin24,Pin25,Pin26,Pin27,Pin30,Pin31,Pin38,Pin39,Pin 46,Pin47,Pin52,Pin53,Pin54,Pin55,Pin56,Pin57,Pin58, Pin59,Pin60,Pin61,Pin62,Pin63 Function Description Analog Normal Output Pad with Resistor 50ohm and Separate Bulk Bias (poar50_bb) Oscillator Cell with Enable and 1Mohm Resistor (psoscm26) LVCMOS Normal Output Buffer (pob2) 5V-tolerant LVCMOS Level Input Buffer (ptic) LVCMOS Schmitt Trigger Level Input Buffer (pic) LVCMOS Tri-State Bi-Directional buffer with Pull-Up (pbcut1) Tri-State Output Buffer (pot2)
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
VDD = 3.3 0.3V, TA = 0 to 70C ( In case of normal IO) Symbol VIH VIL VT VT+ VTParameter High level input voltage (LVCMOS interface) Low level input voltage (LVCMOS interface) Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current IIH Input buffer Input buffer with pull-up Low level input current IIL input buffer Input buffer with pull-up High level output voltage VOH Type B1 to B24 Type B1 Type B2 Low level output voltage VOL Type B1 to B24Note2 Type B1 Type B2 IOZ IOS Tri-state output leakage current Output short circuit current IOH = 1uA IOH = 1mA IOH = 2mA VOUT= VSS or VDD VDD = 3.6V, VO = VDD VDD = 3.6V, VO = VSS IDD CIN COUT Quiescent supply current Input capacitanceNote4 Output capacitanceNote4 VIN = VSS or VDD Any Input and Bidirectional Buffers Any Output Buffer -170 100note3 4 4 uA pF pF -10 10 210 uA mA 0.05 0.4 V
Note2
Condition
Min 2.0
Type
Max
Unit V
0.6 LVCMOS LVCMOS LVCMOS 0.8 1.4 2.0
V
V
VIN = VDD
-10 10 30
10 60
uA
-10 VIN = VSS -60 -30
10 -10
uA
IOH = -1uA IOH = -1mA IOH = -2mA
VDD -0.05 2.4 V
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
VDD = 3.3 0.3V, VEXT = 5+ 0.25V, TA = 0 to 70C ( In case of 5V-tolerant IO) Symbol VIH
Note1
Parameter High level input voltage (LVCMOS interface) Low level input voltage (LVCMOS interface) Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current
Condition
Min 2.0
Type
Max
Unit V
VIL Note1 VT VT+ VT-
0.6 LVCMOS LVCMOS LVCMOS 0.8 1.4 2.0
V
V
IIH
Input buffer Input buffer with pull-up Low level input current
VIN = VDD
-10 10 30
10 60
uA
IIL
input buffer Input buffer with pull-up VIN = VSS VOUT= VSS or VEXT VDD =3.6V, VO=VDD VDD =3.6V, VO=VSS
-10 -60 -10 -30
10 -10 10 55
uA
IOZ IOS
Tri-state output leakage current Output short circuit current
uA mA
-55 100Note3 4 4 uA pF pF
IDD CIN COUT
Quiescent supply current Input capacitance Output capacitance
VIN = VSS or VDD Any Input and Bidirectional Buffers Any Output Buffer
NOTES: 1. All 5V-tolerant input have less than 0.2V hysterisis. 2. Type B1 means 1mA output driver cells, and Type B6/24 means 6mA/24mA output driver cells. 3. This value depends on the customer design. 4. This value exclude package parasitic.
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
OPERATION DESCRIPTION
IO TIMING SPECIFICATION MCU Interface a. Serial interface mode
MCK MLT MDATA SENSEB Register read protocol A0 A1 A2 A3 A4 A5 A6 A7 D7 D6 D5 D4 D3 D2 D1 D0
MCK MLT MDATA D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 Register write protocol register write
burstNum * 16 MCK
MLT MDATA A0 A1 A2 A3 A4 A5 A6 A7 Memory read command (8'h50) SENSEB D15 D14 Memory read protocol BurstLength * 16 MCK MLT MDATA B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7 Burst Length Data memUnit Req. Memory write protocol Memory write command (8'hF4) register write D15 D14 D1 D0 D15 D14 D1 D0 D1 D0 D15 D14 D1 D0
Figure 5. Serial interface mode
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
b. Parallel interface mode
AD ALE OE(out) AckRdB
A[7:4] A[3:0]
D[7:4] D[3:0]
Data load Parallel register read protocol
AD ALE Wrb AckWr(out)
A[7:4]
A[3:0]
D[15:12] D[11:8]
Parallel register write protocol
AD
A[7:4]
A[3:0]
D D[11:8] D[7:4] [15:12]
D[3:0]
D D[11:8] [15:12]
ALE OE(out)
AckRdB
Data load Parallel momory read protocol
D D[11:8] D[7:4] [15:12] D D[11:8] [15:12]
AD ALE
A[7:4] A[3:0]
D[3:0]
Wrb
AckWr(out) memory write done Parallel momory write protocol
Figure 6. Parallel interface mode
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
Description for the memory read protocol 1. 2. 3. 4. Write Start Address to H_MEM_ADDR_HIGH (8'hf0), H_MEM_ADDR_MID (8'hf1), and H_MEM_ADDR_LOW (8'hf2). Write BL(Burst Length) to H_MEM_ADDR_BL (8'hf3). The BL is programmable between 1 and 63. The default value of the H_MEM_ADDR_BL when reset is 1. Send command 8'h50 (i.e. Transfer address of the H_MEM_READ). Read MDOUT as many bits as the " BL*16 ". (16bits per 1 burst, each burst is MSB first.)
Description for the memory write protocol 1. 2. 3. Write Start Address to H_MEM_ADDR_HIGH (8'hf0), H_MEM_ADDR_MID (8'hf1), and H_MEM_ADDR_LOW (8'hf2). Write BL(Burst Length)and memory write command to H_MEM_WRITE (8'hf4). The BL is programmable between 1 and 63. Write MDAT as many bits as the " BL*16 ". (16bits per 1 burst, each burst is MSB first.)
Description for the input buffer write protocol 1. 2. Write BL(Burst Length)and input buffer write command to H_MEM_WRITE_IB (8'hf5). The BL is programmable between 1 and 63. Write MDAT as many bits as the " BL*16 ". (16bits per 1 burst, each burst is MSB first.)
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
CD-DSP Interface (a) 32-bit BCK, MSB First, Right Channel Low, C2PO LSB First, Data Latch Timing High:
BCK
LRCK DATA C2PO 1 0 Invalid
LEFT CHANNEL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RIGHT CHANNEL Invalid LOWER (RIGHT CH.)
LOWER (LEFT CH.)
UPPER (LEFT CH.)
(b) 32-bit BCK, MSB First, Left Channel Low, C2PO MSB First, Data Latch Timing Low:
BCK
LRCK DATA C2PO 1 0 Invalid
RIGHT CHANNEL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEFT CHANNEL Invalid
UPPER (RIGHT CH.)
LOWER (RIGHT CH.)
UPPER (LEFT CH.)
(c) 24-bit BCK, MSB First, Right Channel Low, C2PO MSB First, Data Latch Timing High:
BCK
LRCK DATA C2PO 1 0
LEFT CHANNEL Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid 15 14 13 12 11
UPPER (LEFT CH.)
LOWER (LEFT CH.)
UPPER (RIGHT CH.)
(d) 24-bit BCK, LSB First, right Channel Low, C2PO MSB First, Data Latch Timing Low:
BCK RIGHT CHANNEL
LRCK DATA C2PO 14 15
LEFT CHANNEL Invalid 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Invalid
0
1
2
3
4
UPPER (LEFT CH.)
LOWER (LEFT CH.)
UPPER (RIGHT CH.)
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
(e) 16-bit BCK, MSB First, Left Channel Low, C2PO LSB First, Data Latch Timing High:
BCK LEFT CHANNEL
LRCK DATA C2PO 1
RIGHT CHANNEL 0 15 14 13 12 11 10 9 LOWER (RIGHT CH.) 8 7 6 5 4 3 2 1
0 15 14 13 12 11 10 9 LOWER (LEFT CH.)
8
7
6
5
4
3
2
1
0 15 14 13 12 11 LOWER (RIGHT CH.)
UPPER (RIGHT CH.)
UPPER (LEFT CH.)
(f) 24-bit BCK, MSB First, Right Channel Low, C2PO MSB First, Data Latch Timing Low:
BCK
LRCK DATA C2PO 1 0
LEFT CHANNEL 15 UPPER (LEFT CH.) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RIGHT CHANNEL 15 UPPER (RIGHT CH.) 14 13 12
LOWER (LEFT CH.)
(g) 24-bit BCK, LSB First, Right Channel Low, C2PO LSB First, Data Latch Timing Low:
BCK
LRCK DATA C2PO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 UPPER (LEFT CH.)
LEFT CHANNEL Invalid Invalid 0 1
RIGHT CHANNEL 2 3 4 5 6 7 8 9 10 11
LOWER (LEFT CH.)
LOWER (RIGHT CH.)
UPPER (RIGHT CH.)
Even on the format of description it changes a H_INPIF_W register value and the CD DSP which is various and the interface is possible.
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
DRAM Interface Read Cycle
RAS 2T CAS 1T ADDR 1T 3T COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS 2T 1T
ROW ADDRESS
WE S DATA[3:0] H DATA-OUT DATA-OUT DATA-OUT
DATA-OUT Don't Care, OE = GND, 1T=25ns, S = setup T, H = hold T
Figure 7. Read Cycle Write Cycle
RAS 2T CAS 1T ADDR 1T 3T COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS 2T 1T
ROW ADDRESS
WE
DATA[3:0] D
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
Don't Care, OE = D.C., 1T=25ns, 1D=delay T
Figure 8. Write Cycle
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
RAS Before CAS Refresh
RAS
5T
2T+10ns
CAS
4T
2T+10ns
WE, OE, Data = Don't Care,Don't Care, 1T=59ns
Figure 9. RAS Before CAS Refresh
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
POWER MANAGEMENT
Power Save Modes Down : Master Clock Disabled. Whole chip is in reset state and clocking is disabled. Sleep Mode : All units suspended except hitUnit and DRAM Controller Block to refresh DRAM.
Running
Re
op St
M P3
pla
Pa
Pl ay
y
us e
Power Down
Sleep
System Power ON
Power down mode Power down mode is implemented using MLAT, MCK, and MDAT. When the MLAT is low the MDAT is goes to low, the CD-MP3 goes to "power down reset" mode. It means power ON state. When the MLAT is low and the MCK goes to LOW, the CD-MP3 toggles the "power down mode". The default value of MLAT, MCK, and MDAT is HIGH. When the system power becomes ON and the master reset comes, Micom should set the value of MLAT, MCK, and MDAT to HIGH. And should reset the power down mode of CD-MP3 using MLAT and MDAT LOW. Finally should send the S/W reset to CD-MP3 H_SOFT_RST (8'hE0) register. Sleep mode In sleep mode, the minimal power is supplied which is needed just for DRAM refresh, receiving host command, and etc. There is a register H_SLEEP_CR to control Sleep mode. To enter sleep mode write "1xxxxxxx" into the H_SLEEP_CR. To wake up from sleep mode write "0xxxxxxx" into the H_SLEEP_CR. H_SLEEP_CR Power Save mode In power save mode, hardware units in the S5L9276X can be dynamically enabled or disabled during it's operation to reduce the power consumption. This feature is enabled by writing xxxxxxx1 to H_PSV_ENABLE and disabled by writing xxxxxx0 to H_PSV_ENABLE. Make sure that Power Save mode should be disabled for Micom to access all other S5L9276 registers. H_PSV_ENABLE 8'hde 8'hdf
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
HOST MCU CONTROL SPACE
Registers to control CD-ROM sector decoding // Read only registers (8'h20 8'h2F reserved for cdrUnit - Read) H_MIN_R 8'h24 "minute" in the header of the sector being currently decoded. H_SEC_R 8'h25 "second" in the header of the sector being currently decoded. H_FRM_R 8'h26 "frame" in the header of the sector being currently decoded. H_MODB_R 8'h27 CD-ROM Mode information in the header of the sector being currently decoded. H_FN_R 8'h28 The file number information in the sub header of the current frame. This is valid for Mode-2 format. H_CN_R 8'h29 The channel number information in the sub header of the current frame. This is valid for Mode-2 format. H_SM_R 8'h2a The sub-mode information in the sub header of the current frame. This is valid for Mode-2 format. H_CI_R 8'h2b The coding information in the sub header of the current frame. This is valid for Mode-2 format. H_ERR_R 8'h2c The Header Error flags in the sub header of the current frame. bit7 M_EMIN (Error in MIN) bit6 M_ESEC (Error in SEC) bit5 M_EFRM (Error in FRM) bit4 M_EMOD (Error in MODB) bit3 M_EFN (Error in FN) bit2 M_ECN (Error in CN) bit1 M_ESM (Error in SM) bit0 M_ECI (Error in CI) H_BLKST_R 8'h2d Indicates that unexpected Sync has been detected. bit7 Long Block 0 : Normal case. 1 : The CD-ROM decoder detects the Internal Synchronization pattern but does not detect the External Synchronization pattern. The previous frame has longer bytes of data than expect. bit6 Short Block 0 : Normal case. 1 : The CD-ROM decoder detects the External Synchronization pattern but does not detect the Internal Synchronization pattern. The previous frame has shorter bytes of data than expect. bit5 Invalid Block 0 : Normal case. 1 : The CD-ROM decoder does not detect either External or Internal Synchronization pattern when Internal or External Synchronization pattern is detected. Current frame data is invalid. bit4:0 not used
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
// Write only registers (8'hB0 8'hBF reserved for cdrUnit - Write) H_INPIF_W 8'hB1 bit7 M_BCKS1 bit6 M_BCKS0 bit7:6 Indicate the number of BCKs per 16-bit word 00 = 16 BCKs, Data valid at every BCK 01 = 24 BCKs. Data valid for the last 16 BCKs 10 = 24 BCKs. Data valid for the first 16 BCKs 11 = 32 BCKs. Data valid for the last 16 BCKs bit5 M_DATMF Must be set equal to '1' for the input data with MSB first bit4 M_C2PMF Must be set equal to '1' for the input C2PO with MSB first bit3 M_LRB. Must be set equal to '1' if HIGH of LRCK indicates the left channel. bit2 M_LATCH( not enable ) 1 : Input data is latched on the rising edge of BCK, 0 : Input data is latched on the falling edge of BCK. bit1 M_C2PEN 1 : C2PO data is input with other data, 0 : No C2PO data is input with other data. bit0 M_PHILIPS. When the CD-DSP data format is as PHILIPS', this bit should be a logical '1' 1: Supports PHILIPS' IIS DSP interface format. 0 : Do not supports PHILIPS' IIS DSP interface format. default value : 0x00 H_HEAD_W 8'hB2 MODE1, MODE2-Form1, MODE2-Form2 bit7 Mode2/Mode1 1 : Mode2 0 : Mode1 bit6 Form2/Form1 1 : Form2 0 : Form1 bit5 AC. Auto correction 1 : CD-ROM decoder acts as according to the value of mode/form bits in the header/sub header 0 : CD-ROM decoder acts as according to the value of bit7:6 of this register bit4 DSCR .Descrambling Enable/Disable 1 : Descrambling Enable 0 : Descrambling Disable bit3:0 not used
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
H_OPSR_W
8'hB3 0x00: Set CDROM decoding mode to IDLE mode. CDROM decoder discards all input bit stream and does no decoding. All registers containing decoded header information is not valid in this mode. 0x90: Set CDROM decoding mode to MONITORING mode. Decodes Header only. 0x91: Set CDROM decoding mode to DECODING mode. This causes S5L9276 starts to decode the following sector and store to DRAM. Not Used Not Used Not Used Control register for ECC enable/disable. bit7:1 not used bit0 H : Ecc Enable default value : 0x00
H_START_M H_START_S H_START_F H_ECC_EN
8'hB4 8'hB5 8'hB6 8'hB7
Registers to communicate with embedded DSP core // Read only registers (8'h00 8'h0F reserved for dspUnit - Read) H_OUT1_LOW 8'h01 Low byte of OUT1 register. H_OUT1_HIGH 8'h02 High byte of OUT1 register. H_OUT2_LOW 8'h03 Low byte of OUT2 register. H_OUT2_HIGH 8'h04 High byte of OUT2 register. H_OUT_XTRA 8'h05 Extra byte of OUT register. H_EMPH 8'h06 Indicate Emphasis ON/OFF and Emphasis Type. bit[7:2] : not used. bit[1] : If "1", Emphasis ON. If "0", emphasis OFF. bit[0] : Emphasis Type // Write only registers (8'h80 8'h8F reserved for dspUnit - Write) H_SSPINT 8'h80 Micom command register. Micom writes a command to this register. H_IN_LOW 8'h81 Low byte of in register H_IN_HIGH 8'h82 High byte of in register H_IN_XTRA 8'h83 Extra byte of in register
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S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
Registers for configuration and status of DRAM // Read only registers (8'h10 8'h1F reserved for memUnit - Read) H_DUMP_CNT 8'h11 Total number of CD frames currently has been dumped to DRAM since 0x91 was written to OPSR register. Once all frames as many as specified in the H_FRAME_NO register are dumped into DRAM, OPSR value will be changed to 90 automatically after completion of dump. At every time after 0x91 was written to OPSR and 1 frame has been dumped, the H_DUMP_CNT reset to "1". H_IB_STATE 8'h12 Input Buffer Occupancy bit0 : Empty bit1 : Low bit2 : High H_IB_DATA_COUNT_H 8'h13 The high positive byte of the data count value which is to the input buffer H_IB_DATA_COUNT_M 8'h14 The middle position byte of the data count value which is to the input buffer H_IB_DATA_COUNT_L 8'h15 The low position byte of the data count value which is to the input buffer H_OBL_DATA_COUNT_H 8'h16 The high positive byte of the data count value which is to the OBL buffer H_OBL_DATA_COUNT_M 8'h17 The middle positive byte of the data count value which is to the OBL buffer H_OBL_DATA_COUNT_L 8'h18 The low positive byte of the data count value which is to the OBL buffer H_OBR_DATA_COUNT_H 8'h19 The high positive byte of the data count value which is to the OBR H_OBR_DATA_COUNT_M 8'h1a The middle positive byte of the data count value which is to the OBR buffer H_OBR_DATA_COUNT_L 8'h1b The low positive byte of the data count value which is to the OBR buffer
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OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
// Write only registers (8'h90 8'hAF reserved for memUnit - Write) H_CD_START_H 8'h90 H_CD_START_L 8'h91 H_CD_END_H 8'h92 H_CD_END_L 8'h93 H_IB_START_H 8'h94 H_IB_START_M 8'h95 H_IB_START_L 8'h96 H_IB_END_H 8'h97 H_IB_END_M 8'h98 H_IB_END_L 8'h99 H_OBL_START_H 8'h9a H_OBL_START_M 8'h9b H_OBL_START_L 8'h9c H_OBL_END_H 8'h9d H_OBL_END_M 8'h9e H_OBL_END_L 8'h9f H_OBR_START_H 8'ha0 H_OBR_START_M 8'ha1 H_OBR_START_L 8'ha2 H_OBR_END_H 8'ha3 H_OBR_END_M 8'ha4 H_OBR_END_L 8'ha5 H_REFRESH_INTERVAL 8'ha6 DRAM refresh interval rate bit1:0 00: 624 cycles 01: 608 cycles 10: 576 cycles 11: 480 cycles
23
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
H_DRAMIF_NOE
8'ha7
H_FRAME_NO
8'ha8
H_SHOCK
8'ha9
H_IB_WR_OFFSET
8'haa
H_RETURN_SECTOR
8'hab
H_DRAM_TYPE
8'hac
DRAM Interface Output Enable Control Register bit7 : DRAM Interface Outputs Enable (Active Low.) bit6 0 : don't care The frame as many as specified in this H_FRAME_NO register are dumped into DRAM after every 0x91 is written in the OPSR. OPSR value will be changed to 90 automatically after completion of dump. The maximum value allowed for the H_FRAME_NO is IB size/1024. When detect shock from Micom, it sets this register with the value of "xxxxxxx1". This causes to stop dump operation and deletes frames as many as specified in the H_RETURN_SECTOR register from the Input Buffer. When there's no shock, Micom sets H_SHOCK register with the value of "xxxxxxx0". Input Buffer is in LOW state when the condition below is met :" Input Buffer Vacancy is equal to or less than (Size of Input Buffer - the value in the H_IB_WR_OFFSET) " When occurred the shock, before recognizing with the shock, the case shock where the data which breaks has become the dump in the dram the set it does as a favor the thing authorization which will erase the data of the some frame in standard. If set register clear the H_DUMP_CNT. Define the DRAM type. bit1:0 00: 4Mbit dram 10: 16Mbit dram 2K ref. 11: 16Mbit dram 4K ref.
24
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
Registers to control DAC interface // Read only registers (8'h30 8'h3F reserved for difUnit - Read) // Write only register (8hB0) H_DAC_TYPE 8'hB0 Register H_DAC_TYPE[7]
To control Type of 1bit DAC. Name bck phase Value 0 1 Operation rising edge output data strobe falling edge output data strobe If lrck is 'L', data is R-channel. If lrck is 'H', data is R-channel. 32 Fs 48 Fs 64 Fs Don't use 16 18 20 24 I2S justify right justify left justify Don't use
H_DAC_TYPE[6]
lrck phase
0 1
H_DAC_TYPE[5:4]
num of bck per lrck
00 01 10 11
H_DAC_TYPE[3:2]
num of real data
00 01 10 11
H_DAC_TYPE[1:0]
real data position(justify)
00 01 10 11
// Write only registers (8'hC0 8'hCF reserved for difUnit - Write) H_DACIF_nOE 8'hC0 To control Tri-State Output of difUnit. bit7 : If "1", DAC Interface outputs goes high impedance state. If "0", DAC Interface outputs enabled. bit6 0 : don't care To control type of DAC data array bit6 : If "1", the type of DAC is LSB first. If "0", that is MSB first. bit5 0 : don't care
25
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
Registers for configuration of clock // Read only registers (8'h40 8'h4F reserved for ckgUnit - Read) // Write only registers (8'hD0 8'hDF reserved for H_PLL0_P0 8'hd0 H_PLL0_M0 8'hd1 H_PLL0_S0 8'hd2 H_PLL1_P1 8'hd3 H_PLL1_M1 8'hd4 H_PLL1_S1 8'hd5 H_CKG_DIV_XY 8'hd6 H_CKG_CMD_0 8'hd7 H_SLEEP_CR 8'hdf ckgUnit) P register for PLL0 (See chapter 7.) M register for PLL0 (See chapter 7.)) S register for PLL0 (See chapter 7.)) P register for PLL1 (See chapter 7.)) M register for PLL1 (See chapter 7.)) S register for PLL1 (See chapter 7.)) (See chapter 7.)) (See chapter 7.)) SLEEP control register bit7 1 : don't care bit0 : If "1", Set S5L9276 to SLEEP mode. If "0", set S5L9276 to RUNNING mode.
Registers for reset control // Write only registers (8'hE0 8'hEF reserved for rstUnit - Write) H_SOFT_RST 8'hE0 Master reset by software control Registers for DRAM access and Interrupt Source Register // Read only registers (8'h50 8'h5F reserved for hifUnit - Read) H_MEM_READ 8'h50 Buffer Register for DRAM burst read H_INT_READ 8'h51 Interrupt Source Register // Write only registers (8'hF0 8'hFF reserved for H_MEM_ADDR_HIGH 8'hf0 H_MEM_ADDR_MID 8'hf1 H_MEM_ADDR_LOW 8'hf2 H_MEM_ADDR_BL 8'hf3 H_MEM_WRITE 8'hf4 H_MEM_WRITE_IB 8'hf5 hifUnit - Write) High byte of start address for DRAM burst read Middle byte of start address for DRAM burst read High byte of start address for DRAM burst read Burst Length for DRAM burst read (1 63, default is 1.) Buffer Register for DRAM burst write Buffer Register for Input Buffer in DRAM burst write
26
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
SETTING SYSTEM CLOCK FREQUENCY PLL configuration should be changed in the SLEEP mode only. To change PLL configuration, 1. enter to SLEEP mode. 2. change PLL configuration. 3. wait 250ms. 4. exit from SLEEP mode.
NOTE : ACLK : audio clock of S5L9276X internal. CLK : system clock of S5L9276X internal.
MODE 1 - Dual PLL Mode A ( H_CKG_CMD0[2:1] = 01 or 00 , PLL_BYPASS = LOW)
aclk = 12.288MHz clk = 38.7MHz aclk = 16.9344MHz clk =38.7MHz aclk = 18.432MHz clk = 38.7MHz
H_PLL0_P0 H_PLL0_M0 H_PLL0_S0 Host Control H_PLL0_P1 H_PLL0_M1 H_PLL0_S1 H_CKG_DIV_XY H_CKG_CMD0 CLK (I) PIN SETTING ACLK_EXT (I) XI XO
19 (D) 40 (D) 0 (D) 5 (D) 12 (D) 0 (D) xx11 xx00 (B) 0000 0010 (B)
19 (D) 40 (D) 0 (D) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) 0000 0000 (B) CONNECTED TO XOUT TIED TO GND 16.9344MHz X-tal 16.9344MHz X-tal
19 (D) 40 (D) 0 (D) 5 (D) 22 (D) 0 (D) xx11 xx00 (B) 0000 0010 (B)
27
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
MODE 2 - Dual PLL Mode B ( H_CKG_CMD0[2:1] = 01 or 00 , PLL_BYPASS = LOW)
aclk = 12.2919MHz clk = 32.33MHz aclk = 16.9344MHz clk = 32.33MHz aclk = 18.4378MHz clk = 32.33MHz
H_PLL0_P0 H_PLL0_M0 H_PLL0_S0 Host Control H_PLL0_P1 H_PLL0_M1 H_PLL0_S1 H_CKG_DIV_XY H_CKG_CMD0 CLK (I) PIN SETTING ACLK_EXT (I) XI XO
20 (D) 34 (D) 0 (D) 10 (D) 65 (D) 3 (D) xx01 xx00 (B) 0000 0010 (B)
20 (D) 34 (D) 0 (D) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) 0000 0000 (B) CONNECTED TO XOUT TIED TO GND 16.9344MHz X-tal 16.9344MHz X-tal
20 (D) 34 (D) 0 (D) 14 (D) 65 (D) 2 (D) xx01 xx00 (B) 0000 0010 (B)
28
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
MODE 3 - Single PLL Mode ( H_CKG_CMD0[2:1] = 10 or 00 , PLL_BYPASS = LOW)
aclk = 12.3159MHz clk = 36.9MHz aclk = 16.9344MHz clk =38.7MHz aclk = 18.407MHz clk = 36.8MHz
H_PLL0_P0 H_PLL0_M0 H_PLL0_S0 Host Control H_PLL0_P1 H_PLL0_M1 H_PLL0_S1 H_CKG_DIV_XY H_CKG_CMD0 CLK (I) PIN SETTING ACLK_EXT (I) XI XO
20 (D) 40 (D) 0 (D) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xx10 xxxx (B) 0000 0100 (B)
19 (D) 40 (D) 0 (D) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) 0000 0000 (B) CONNECTED TO XOUT TIED TO GND 16.9344MHz X-tal 16.9344MHz X-tal
21 (D) 42 (D) 0 (D) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xx01 xxxx (B) 0000 0100 (B)
MODE 4 - PLL BYPASS Mode (PLL_BYPASS = HIGH)
aclk = External Source (ACLK_EXT) clk = External Source (CLK)
H_PLL0_P0 H_PLL0_M0 Host Control H_PLL0_S0 H_PLL0_P1 H_PLL0_M1 H_PLL0_S1 H_CKG_DIV_XY H_CKG_CMD0 CLK (I) PIN SETTING ACLK_EXT (I) XI XO
xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) System Clock Frequency Audio Clock Frequency (384Fs) TIED TO GND OPEN
29
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
MICOM PROGRAMMING GUIDELINE
Transferring Input Bit stream to S5L9276 Micom is allowed to initiate the transfer when the Input Buffer is in LOW state which is by the "Input Buffer State" Interrupt (See section skip function) from CD-MP3 IC. Burst Transfer with the number of sectors being transferred. Verify the Input Buffer is in LOW state. The register H_IB_STATE tells Input Buffer (Empty, Low, or High). When there is any change in the H_IB_STATE, "Input Buffer " Interrupt arises, and External MCU can read the H_IB_STATE to know the Input State. When Input Buffer is in lower than the "Input Buffer Low Threshold" we say is in LOW state. Input Buffer Low Threshold is determined by the value of the register _IB_WR_OFFSET. It has the following relationship. Low Threshold = (Input Buffer Size in number of words) - (H_IB_WR_OFFSET)*1024 Micom decides the start sector address from which the CD-ROM sectors are transferred S5L9276. Write number of sectors being transferred into H_FRAME_NO register. Micom initiate to transfer CD-ROM sectors from CDP subsystem to S5L9276 starting the address (MSF) which is several sectors ahead the start sector address. Micom gets sector address information (MSF) from CDP subsystem while CDP transfers CD-ROM sectors to S5L9276. Micom checks continuously if the MSF received from CDP subsystem is reached at the MSF from which Micom wants to put the corresponding sector in S5L9276. If the MSF received from CDP subsystem is reached at (the start MSF - 1), Micom "0x91" to H_OPSR_W in S5L9276 to allow for S5L9276 to start decode sectors when sector boundary is reached. When "Dump-End" interrupt encountered during sector transfer, read the H_DUMP_CNT and check if the content of the H_DUMP_CNT is equal to the content of _FRAME_NO. If they are equal, it indicates all sectors have been transferred successfully if they are not, it indicates that Input Buffer High condition were met in the middle of transfer and the remaining transfer has been discarded after that condition. If that n has occurred, Micom should transfer again from the sector which was cancelled. new start sector address can be calculated with the previous start sector address and content of the H_DUMP_CNT register. * S5L9276 set the "Dump-End" interrupt when the content of the H_DUMP_CNT is equal to content of H_FRAME_NO and also when Input Buffer High condition were met during transfer.
30
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
Burst Transfer without the number of sectors being transferred. Verify the Input Buffer is in LOW state. The register H_IB_STATE tells Input Buffer (Empty, Low, or High). When there is any change in the H_IB_STATE, "Input Buffer " Interrupt arises, and External MCU can read the H_IB_STATE to know the Input State. When Input Buffer is in lower than the "Input Buffer Low Threshold" we say is in LOW state. Input Buffer Low Threshold is determined by the value of the register _IB_WR_OFFSET. It has the following relationship. Low Threshold = (Input Buffer Size in number of words) - (H_IB_WR_OFFSET)*1024 Micom decides the start sector address from which the CD-ROM sectors are transferred S5L9276. Write 0 to the H_FRAME_NO. (The default value after reset this is 0 therefore, this would not be necessary.) Micom initiate to transfer CD-ROM sectors from CDP subsystem to S5L9276 starting the address (MSF) which is several sectors ahead the start sector address. Micom gets sector address information (MSF) from CDP subsystem while CDP transfers CD-ROM sectors to S5L9276. Micom checks continuously if the MSF received from CDP subsystem is reached at the MSF from which Micom wants to put the corresponding sector in S5L9276. If the MSF received from CDP subsystem is reached at (the start MSF - 1), Micom "0x91" to H_OPSR_W in S5L9276 to allow for S5L9276 to start decode sectors when sector boundary is reached. When "Dump-End" interrupt encountered during sector transfer, it indicates the input is in BUFFER-HIGH state and any more transfer is discarded to avoid input buffer . Read the H_DUMP_CNT register which represents the number of sectors that have successfully transferred. Micom calculate new start sector address which is the one for the next to the last which has been transferred before. Repeat the whole process.
31
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
CDFS Table Read S5L9276X decodes File Allocation Table of CD-ROM and stores it to DRAM. Micom can access DRAM to read the CDFS Table using register read protocol. Setting DRAM Refresh Rate Micom can change DRAM refresh rate by change a code in the H_REFRESH_INTERVAL register as following : H_REFRESH_INTERVAL(8'ha2) VALUE 8'bxxxxxx00 8'bxxxxxx01 8'bxxxxxx10 8'bxxxxxx11 Configuration of DRAM Memory Map When S5L9276 is reset the DRAM is configured to the default memory map as shown below. Maximum Refresh Interval 624 cycles 608 cycles 576 cycles 480 cycles
H_CD_START H_CD_END H_IB_START
<4Mbit DRAM> 0x00000 CD-ROM Decoder Working Buffer 0x00DB6 Not Used 0x01000
H_CD_START H_CD_END H_IB_START
<16Mbit DRAM> 0x00000 CD-ROM Decoder Working Buffer 0x00DB6 0x01000 Not Used
Input Buffer H_IB_END H_OBL_START 0x19FFF 0x1A000 Output Buffer L-CH H_OBL_END H_OBR_START H_OBR_END 0x280FF 0x28100 Output Buffer R-CH 0x361FF 0x36200 0x3FFFF H_OBR_END Reserved 0xF61FF 0xF6200 0xFFFFF H_IB_END H_OBL_START H_OBL_END 0xF34FF 0xF3500
Input Buffer
0xF4B7F H_OBR_START 0xF4B80
Output Buffer L-CH
Output Buffer R-CH Reserved
Figure 10.
32
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
REGISTER H_CD_START H_CD_END
ADDRESS (HEX) 0x00000 0x00DB6 0x00DB7 0x00FFF
ADDRESS (DEC) 0 3510 3511 4095 4096 106495 106496 164095 164096 221695 221696 262143
SIZE Size = 3511
585 words Not Used IB_Size = 100K
H_IB_START H_IB_END H_OBL_START H_OBL_END H_OBR_START H_OBR_END
0x01000 0x19FFF 0x1A000 0x280FF 0x28100 0x361FF 0x36200 0x3FFFF
OBL_Size = 57600
OBR_Size = 57600
40448 Words Reserved
A storage for CDFS Table which is decoded by S5L9276 is needed for Micom to access. CDFS Table also stored in OBR(Output Buffer Right Channel) and OBL(Output Buffer Channel). S5L9276 provides memory map switching mechanism which enables of the OBR(Output Buffer Right Channel) Map between CDFS decoding and decoding modes. In CDFS decoding mode OBR and OBL are allocated outside of location of them in MP3 decoding mode to keep the CDFS table does not overlap the audio output buffer. Micom can access CDFS Table any time if necessary.
Memory Map for CDFS Decoding H_CD_START H_CD_END H_IB_START 0x01000 Input Buffer H_IB_END 0x19FFF 0x1A000 0x00000 CD-ROM Decoder Working Buffer H_CD_START H_CD_END H_IB_START
Memory Map for MP3 Decoding 0x00000 CD-ROM Decoder Working Buffer 0x01000
Input Buffer H_IB_END H_OBL_START 0x334FF 0x33500
Reserved
0x34B7F H_OBR_START 0x34B80 H_OBR_END 0x361FF 0x36200 0x3FFFF
H_OBL_END
Output Buffer L-CH Output Buffer R-CH
H_OBR_START H_OBR_END H_OBL_START H_OBL_END
0x361FF 0x36200
Output Buffer R-CH Output Buffer L-CH
Reserved
0x3FFFF
Figure 11. Memory Map Configuration for 4Mbit DRAM
33
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
Memory Map for CDFS Decoding H_CD_START H_CD_END H_IB_START 0x00000 0x01000 CD-ROM Decoder Working Buffer H_CD_START H_CD_END H_IB_START
Memory Map for MP3 Decoding 0x00000 CD-ROM Decoder Working Buffer 0x01000
Input Buffer H_IB_END 0x19FFF 0x1A000
Input Buffer H_IB_END H_OBL_START 0xF34FF 0xF3500
Reserved
H_OBL_END
0xF4B7F H_OBR_START 0xF4B80 H_OBR_END 0xF61FF 0xF6200 0xFFFFF
Output Buffer L-CH Output Buffer R-CH
0xF61FF H_OBR_START 0xF6200 H_OBR_END H_OBL_START H_OBL_END 0xFFFFF
Output Buffer R-CH Output Buffer L-CH
Reserved
Figure 12. Memory Map Configuration for 16Mbit DRAM
34
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
Data Structure of CDFS Table in DRAM Data Structure of CDFS Table divided into four area : The Introduction Table Area, Table Area, File Table Area and Identifier Table Area. According to Figure , is a typical configuration of DRAM, Output Buffer R-CH and Output Buffer L-CH are to store all CDFS Tables when S5L9276 is in the CDFS decoding mode. The Area, Directory Table Area and File Table Area are located in the Output R-CH. The Identifier Table Area is located in the Output Buffer L-CH. H_OBR_START 0xF6200 Introduction table Directory table File table H_OBR_END H_OBL_START 0xF6FFF 0xF7000 Identifier table H_OBL_END 0xFFFFF Output Buffer L_CH Output Buffer R_CH
Introduction Table Table consists of 4 words (1 word = 16bits). This Table is located in the top the Output Buffer R-CH. Address 36200 36201 36202 36203 Contents (16 bits) Total number of directories in a CD Total number of MP3 files in a CD Total number of directories which contains any MP3 file in a CD The directory number which contains the 1'st MP3 file in the whole directory path. The directory number is assigned for each directory in the order of sequence in the file system structure.
35
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
Directory Table Directory Table follows the Introduction Table and comprises of consecutive directory records. There are as many directory records as the total number of directories in a table. Each directory record consists of 6 words as following. Address 36204+6i Contents (16 bits) The 1'st MP3 file number in this directory. (if there is no MP3 files in this directory, this represents the 1'st MP3 file number in next directory) 36205+6i The total number of MP3 files in this directory (Zero if there is no MP3 files in this directory.) 36206+6i 36207+6i 36208+6i 36209+6i Directory identifier length Parent directory number Sub directory number Next directory number
i : 0 (total number of directories-1) All directories in a CD are given directory number which is a series of number from 1 to number of the total directory count. Directories has no MP3 files also given number and included in the directory table. Therefore root directory is always directory number 1. An explanation is given below about the relationship between directory, sub directory and next directory with example :
/1
/2
/4 /5 /8 /9
/3
/6
/A
/C /D
/7
/B
directory number parent directory sub directory next directory
1 1 1 1
2 1 4 3
3 1 6 2
4 2 4 5
5 2 8 4
6 3 A 7
7 3 7 6
8 5 8 9
9 5 9 8
A 6 C B
B 6 B A
C A C D
D A D C
36
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
File Table File Table follows the Directory Table and comprises of consecutive file records. In the table, there are as many file records as the total number of MP3 file. Each file record of 6 words as following. Address 36204 + Nd*6 +6j 36204 + Nd*6 +6j +1 36204 + Nd*6 +6j +2 36204 + Nd*6 +6j +3 36204 + Nd*6 +6j +4 36204 + Nd*6 +6j +5 Nd : total number of directories j: 0 (Nf-1) , Nf = total number of MP3 files There is no file record for a non-MP3 file. M, S, and F are the values indicating 1 sector before to the actual sector address beginning of a file. A file length is described as 8 hex digits (L8 L1). The length represented is FFFFFFFF. The value of M, S, and F which are all 0xAA or 0xBB indicates End of File Table data. Identifier Table Table is stored in the Output Buffer CH-L. Because the maximum length of or file identifier is 128 bytes both of the identifiers occupy 64(40h) words in DRAM . The directory identifiers comes first and file identifiers follow the directory . The first directory identifier occupies address 37000h 3703Fh in DRAM. The addresses of each directory identifier (=X) are calculated as following : X = F7000h + i * 40h , i : 0 (Nd - 1) L8 L4 M 0x00 L7 L3 L6 L2 Contents S F L5 L1
MP3 file identifier length MP3 file type
The start addresses of each file identifiers (=Y) are calculated as following : Y = F7000h + (nd * 40h) + j * 40h , j = 0 (Nf - 1)
Boot Process Programming 1. Power on CD-MP3 IC #initial #25ns(min) #25ns(min) #25ns(min) #25ns(min) i_MLT=i_MDAT=i_MCK=HIGH i_MLT <= LOW i_MDAT <= LOW i_MDAT <= HIGH i_MLT <= HIGH
When the system is powered-on and the "power-on reset" comes, Micom should set the of MLT, MCK, and MDAT to 1'b1. When the MLT is low and the MDAT goes to low, the S5L9276 enters to "power-off" mode. Make sure to initialize the power mode to "power-off" mode at first. And then the power-on process shown below is the next process required for S5L9276 to be powered on.
37
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
#initial #25ns(min) #25ns(min) #25ns(min) #25ns(min)
i_MLT=i_MDAT=i_MCK=HIGH i_MLT <= LOW i_MCK <= LOW i_MCK <= HIGH i_MLT <= HIGH
At every supply of MCK pulse (active LOW) the mode is toggled between power-on and -off.
MLT MDAT MCK initialize power mode to "power-off".
toggle power on/off
toggle power on/off
PWRDNB power on power off
Power On/Off Control Protocol
2. S/W reset Send Software Reset to CD-MP3 by writing to H_SOFT_RST(8'hE0) with 8'bxxxxxx01. After several system cycles Software Reset automatically cleared. Make sure that S/W reset should be asserted twice with the time interval of 250ms. (PLL is reset in the first S/W reset, and wait for 250ms to settle the PLL frequency and after that, assert second S/W reset to accomplish the S5L9276 reset.) 3. enable DRAM interface output drivers H_DRAMIF_NOE 4. configuration of ckgUnit To configure ckgUnit to Mode1 44.1kHz, for example, 1. Enter to SLEEP mode 2. Configure PLL H_PLL0_P0 H_PLL0_M0 H_PLL0_S0 H_PLL0_P1 H_PLL0_M1 H_PLL0_S1 H_CKG_DIV_XY H_CKG_CMD_0 3. Wait longer than 250ms. 4. Exit from SLEEP mode (8'hD0) (8'hD1) (8'hD2) (8'hD3) (8'hD4) (8'hD5) (8'hD6) (8'hD7) * 8d'19 * 8d'40 * 8d'0 * don't care * don't care * don't care * don't care * 8d'0 (8'hA7) * 8'b0xxxxxxx
38
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
5.
Set DAC Type H_DAC_TYPE (8'hB0) *8'h91 for DAC in S5L9288
6.
Set CDP Type H_INPIF_W H_HEAD_W H_ECC_EN (8'hB1) (8'hB2) (8'hB7) * 8'h72 * 8'h18 * 8'bxxxxxxx1 // for SAMSUNG CD-DSP chip // for MODE1 FORM1 // Enable ecc
7. enable DAC interface output drivers and set type of DAC data array to MSB-first H_DACIF_nOES 8. set DRAM refresh interval H_REFRESH_INTERVAL (8'hA6) * 8'bxxxxxx00 We can select one of the four preset refresh interval value. 9 Set DRAM Type 0x00 : 4Mbit DRAM 0x02 : 16Mbit 2Kref DRAM 0x03 : 16Mbit 4Kref DRAM (8'hAC) *8'b00000000 (8'hC0) * 8'b00xxxxxx
39
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
CDFS Decode Process Programming 1. 2. Boot Process Set Memory Map Address for File Table
(Set map for output buffers as following, as an example for 16M DRAM:) H_OBL_START_L H_OBL_START_M H_OBL_START_H H_OBL_END_L H_OBL_END_M H_OBL_END_H H_OBR_START_L H_OBR_START_M H_OBR_START_H H_OBR_END_L H_OBR_END_M H_OBR_END_H (8'h9C) (8'h9B) (8'h9A) (8'h9F) (8'h9E) (8'h9D) (8'hA2) (8'hA1) (8'hA0) (8'hA5) (8'hA4) (8'hA3) *8'h00 *8'h70 *8'hXf *8'hFF *8'hFF *8'hXf *8'h00 *8'h62 *8'hxf *8'hff *8'hff *8'hff
We must note that upper 4 bits of H_OBR_END_H should be 1111 to indicate end of memory map transmission. 3. Wait for Interrupt
When interrupted read H_INT_READ register to identify interrupt type. H_INT_READ 4. (8'h51) * 8'bxxx010xx that indicates re-map done successfully.
Check CD-ROM format and if it is mode2-form2 send a command "8'h0D" . H_SSPINT (8'h80 ) * 8'h0D Mode2Form2
S5L9276 regards files with extension of ".mp2" or ".mp3" as MP3 audio files by default and generates File System Table which includes information of files with those file extensions only. But files with the extension of ".mpg" may also be regarded as MP3 audio files by sending a command "8'h0F". H_SSPINT 5. Send a Command DECODE_CDFS. (8'h80 ) * 8'h0F FATmpAllOK
H_SSPINT (8'h80 ) * 8'h02 is DECODE_CDFS This cause interrupting ssp1611 for ssp1611 to know CD-ROM sectors with CDFS Table will be put into the input buffer. 6. 7. Transfer CD-ROM sectors to S5L9276 in the way described in Section transferring input bit stream. During the sector transfer in step 5, check if "Sending MSF" Interrupt has been received. H_INT_READ (8'h51) *8'bxxx001xx : Sending MSF Interrupt (See section skip function)
After receiving interrupt, Micom should get next sector address by reading the registers below :
40
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
H_OUT1_LOW H_OUT1_HIGH H_OUT2_LOW
(8'h01) (8'h02) (8'h03)
*S *M *F
If M, S and F read are all AAh or BBh, it indicates CDFS decoding has been completed. If they are all AAh it indicates that this CD is not in a juliet format. If they are all BBh it indicates that CD is in joliet format CD. If M, S and F are not all AAh or BBh go to step 8. 8. 9. Transfer CD-ROM sectors to S5L9276 in the way described in Section transferring input bit stream with the start sector address MSF. Repeat 6,7,8.
10. During step 9, When there is an error in the sector received i.g. if the file system is not in accordance with ISO9660, S5L9276 asks the sector again to the Micom. if this happens repeatedly, this means that there is a non-recoverable error in the . In this case micom sends FATnextDIR command for S5L9276 to give up decoding the file system information for the current search path and it's sub-tree. Receiving this command, S5L9276 asks Micom new sector for the next search path of the file system. H_SSPINT (8'h80 ) * 8'h0E FATnextDIR
When CDFS decoding is completed successfully, decoded CDFS tables are stored in such a way described in Section. Data Structure of CDFS Table in DRAM . Micom can read the tables any time. In the Identifier Table, 64 words are allocated to directory or file identifiers. Because 2 bytes are required to represent 1 character Joliet format, maximum 64 characters can be stored in each 64 words of an identifier. in DOS format, because 1 character is represented by 1 byte code, maximum 128 can be stored in each 64 words of identifier. Micom should know if a CD is Joliet format or not to recognize the identifier correctly.
41
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
TAG DECODE PROCESS ID3 TAG Version 1.xx 1. 2. 3. 4. 5. 6. Boot Process Re-map : Configure Memory Map Transfer the last sector of an MP3 file to S5L9276. Write a sector size to registers IN1.
Issue the command DECODE_TAG. Waits interrupt 8'bxxx001xx H_INT_READ (8'h51) *8'bxxx001xx : DECODE_TAG Acknowledge
7. 8.
Read OUT1. If the content of OUT1 is 0xDD01, it indicates there is no TAG in the sector. If the TAG information is found, the content of OUT1 is DRAM of the start of TAG information. If TAG is found, Micom reads DRAM to decode the TAG ins formation.
ID3 TAG Version 2.xx 1. 2. 3. 4. 5. Boot Process Remap : Configure Memory Map Transfer the first sector of an MP3 file to S5L9276.
TAG Information follows ID3 characters therefore Micom can read 3 bytes of the first to decide if there is TAG information in the MP3 file. Micom reads DRAM to decode TAG information.
MP3 decode process 1. 2. Boot Process Re-map : set memory map address for output buffer ( returns memory map to MP3 CDFS decode mode by writing back the default value for output buffer channel. ) H_OBR_START_L H_OBR_START_M H_OBR_START_H H_OBR_END_L H_OBR_END_M H_OBR_END_H (8'hA2) (8'hA1) (8'hA0) (8'hA5) (8'hA4) (8'hA3) *8'h00 *8'h81 *8'hx2 *8'hff *8'h61 *8'hf3 mode from
We must note that upper 4 bits of H_OBR_END_H should be 1111 to indicate end of map transmition. 3. Wait for Interrupt H_INT_READ (8'h51) * 8'bxxx010xx that indicates remap done successfully.
wait for interrupt from ssp1611 that indicates CD-MP3 chip has successfully the remap sequence. When Micom reads H_INT_READ register the interrupt be cleared automatically.
42
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
4.
Send Command DECODE_MP3. H_SSPINT (8'h80 ) * 8'h03 is DECODE_MP3
5. 6.
Micom reads CDFS Table and select a music to be play. Micom set Total_Sector_Number as follows. Total_Sector_Number is a value with 20bit range. H_IN_XTRA (8'h83) : XYZW XXXX Y : if FF(Fast Forward) state when going to next song, set Y=1 Z : if FB(Fast Backrward) state when going to next song, set Z=1 W: if CD-ROM format is Form2, W=1 XXXX: Total_Sector_Number[19:16] : Total_Sector_Number[15:8] : Total_Sector_Number[7:0]
H_IN_HIGH H_IN_LOW 7. 8.
(8'h82) (8'h81)
Transfer CD-ROM sectors to S5L9276 in the way described in Section transferring input bitstream. S5L9276 starts decoding of input bitstream. When audio sampling frequency information the bitstream header S5L9276 writes it to the register H_OUT1_LOW and interrupt . And then S5L9276 stops it's decoding. S5L9276 will resume it's decoding after configures audio clock frequency. When interrupted from S5L9276 for audio frequency information transfer, Micom reads the sampling frequency information in H_OUT1_LOW (8'h01) and set audio clock in S5L9276. H_INT_READ H_OUT1_LOW (8'h51) (8'h01) * 8'bxxx011xx that indicates sending audio sampling frequency code * frequency code
Sampling Frequency Information 000 : 44.1 kHz 001 : 48 kHz 010 : 32 kHz 011 : Not Used 100 : 22.05 kHz 101 : 24 kHz 110 : 16 kHz After setting audio clock frequency Micom send a command (0x23) to S5L9276 to indicate clock frequency setting completed successfully. H_SSPINT (8'h80) * 8'h23 is completion of frequency setting
9. When both of input buffer and output buffer are empty it means that end-of-song S5L9276 is in IDLE state.
Micom can see when input buffer becomes empty S5L9276 interrupts Micom when input buffer state has been changed. Micom can a certain time until output buffer becomes empty when Micom can conclude that -of-song reached. Therefore Micom should keep in mind the last sector has been sent S5L9276 and from that time it checks input buffer state at each interrupts.
43
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
Skip Function 1. 2. 3. Micom controls servo system to stop feeding CD data to S5L9276. Micom send a command "Pause". (This is for the purpose of audio fade-out.) H_SSPINT (8'h80) * 8'h07 (Pause) Follow the sequence from step2 (Re-map) of the "MP3 decode process".
Fast Forward Function 1. 2. 3. Micom writes "number of frame to be skipped" to H_IN_LOW , and "number of frames be decoded" to H_IN_HIGH. Micom send a command FAST FORWARD. Micom send a command REPLAY to return to normal play.
Fast Backward Function At starting Fast Backward, Input Buffer could contain less than 10 sec of input bitstream. Input Buffer should be empty to reverse without delay caused by this input bitstream. 1. Micom send a command "Input Buffer Clear" H_SSPINT 2. (8'h80 ) * 8'h06 is Input Buffer Clear
Micom determine Skip_Sector_Number and Dump_Sector_Number. Micom writes ratio of Skip_Sector_Number and Dump_Sector_Number to H_IN_LOW ( that is Skip_Sector_Number/Dump_Sector_Number) and writes 0 to H_IN_HIGH. Micom send a command "FAST BACKWARD". H_SSPINT (8'h80 ) Micom waits for interrupt * 8'h0A is FAST BACKWARD.
3. 4.
H_INT_READ (8'h51) * 8'bxxx110xx that indicates input buffer cleared. After receiving interrupt, Micom should get Rewinded_Sector_Number by reading the shown below : H_OUT1_LOW (8'h01) * H_OUT1_HIGH (8'h02) * Micom convert Rewind_Sector_Num to Rewind_MSF Micom update Dump_Start_MSF by subtracting Dump_Curr_MSF with Rewind_MSF Micom start to dump at Dump_Start_MSF repeating dump and skip. dump as much as Dump_Sector_Number and skip as much as Skip_Sector_Number. Micom send a command REPLAY to return to normal play.
5. 6. 7. 8.
44
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
Get Decoding Time for Display Wait interrupt continuously during decoding process for time display. H_INT_READ (8'h51) *8'bxxx111xx that indicates S5L9276 send Current_Decoding_Sec
S5L9276 send this interrupt about twice or three times per second. The exact period is determined by sampling frequency. but Micom doesn't need to know the period becase send Current_Decoding_Sec (in second) when interrupt. Micom only have to Current_Decoding_Sec. After receiving interrupt, Micom should get Current_Decoding_Sec (hexa value) by reading the registers shown below : H_OUT1_LOW H_OUT1_HIGH (8'h01) (8'h02) * *
Micom would better display Current_Decoding_Sec in the format of minute: second than second. Set Current Decoding Time with Current Sector Number During Fast Forward or Fast Backward, S5L9276 cannot send correct decoding time of skipped frames. But Micom can update decoding time correctly by sending number currently being decoded. 1. 2. Micom writes lower byte of "sector number currently decoded" to H_IN_LOW and higher byte of "sector number currently decoded" to H_IN_HIGH. Micom send a command "Set Current Decoding Time with Sector Number". H_SSPINT (8'h80 ) * 8'h11 is "Set Current Decoding Time with Sector Number".
Form that time, S5L9276 send new Current_Decoding_Sec converted from "the sector currently decoded" set by Micom. Compute Total Time Total_Sector_Number was set in the way, Micom can call "Compute Time" to get total play time. 1. 2. Micom send command "Compute Total Time". H_SSPINT Micom wait interrupt. H_INT_READ (8'h80 ) (8'h51) * 8'h10 (Compute Total Time) *8'bxxx110xx that indicates S5L9276 send total time in second
After receiving interrupt, Micom should get Total_Sec (hexa value) by reading the shown below : H_OUT1_LOW H_OUT1_HIGH (8'h01) (8'h02) * *
Micom would better display Total_Sec in the format of minute: second than second.
45
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
Display CDFS decoding state Micom can display how much directories and mp3 files is decoded. In CDFS decoding process, after receiving Sending MSF interrupt, Micom should get next sector address by reading the registers shown below H_OUT1_LOW (8'h01) H_OUT1_HIGH (8'h02) H_OUT2_LOW (8'h03) And then, 1. Micom send command "FAT decode H_SSPINT (8'h80 ) *S *M *F State" after saving MSF record. * 8'h19 (FAT decode State)
2. Micom read decoding states H_OUT1_LOW H_OUT1_HIGH H_OUT2_LOW Interrupt handling There is one signal line for interrupt from S5L9276 to Micom (MINT). When Micom is interrupted by S5L9276, it should read the interrupt source register in CD-MP3 (H_INT_READ 8'h51) which indicates the interrupt type to identify which interrupt service should be done. H_INT_READ b7 b6 b5 b4 b3 b2 b1 b0 (8'h01) (8'h02) (8'h03) * No. of song low * No. of song high * No. of directory
b7 : Not Used. (always LOW.) b6 - b5 : cdrUnit Interrupt Source b4 - b2 : dspUnit Interrupt Source b1 - b0 : memUnit Interrupt Source cdrUnit Interrupt Source Description : xx1 : Header Error (When S5L9276 detects error in header of a CD-ROM sector this interrupt is set.) x1x : Sector Address Decoded Out of Range (Discard this in current version of S5L9276.) 1xx : EDC Error dspUnit Interrupt Source Description : 001 : Sending M.F.S This interrupt bits are set when S5L9276 expects to get CD-ROM sectors which is in jumped address from the current sector address during the CDFS decoding. (End Of CDFS Decoding is indicated by M.F.S = all zero.) 010 : End of REMAP 011 : Sending Audio Sampling Frequency Code 100 : reserved 101 : Sending Output Buffer Left Channel Empty Signal 110 : End of Input Buffer Clear / Sending Total Time in second 111 : Sending Decoding Time for Display memUnit Interrupt Source Description : 01 : Dump-End 10 : Input Buffer State 11 : reserved for future use.
46
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
Command Set Description Micom can send a command to S5L9276 by writing a command ID to H_SSPINT register. H_SSPINT (8'h80) b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 : Host Command ID Host Command IDs --------------------------0x01 : DECODE_TAG 0x02 : DECODE_CDFS 0x03 : DECODE_MP3 0x04 : End of Input, indicates last data of MP3 bitstream for current music has been supplied. 0x05 : An Interrupt indicating that Micom completed audio clock frequency setting in response of audio sampling frequency information which is sent to Micom by ssp1611. ssp1611 should wait this interrupt to continue decoding after audio sampling frequency has been changed. In addition to this interrupt, ssp1611 should also wait until the output buffer becomes empty to ensure audio DAC responds correctly at the boundary of different sampling frequency boundary. 0x06 : Clear Input Buffer (This command should be issued before Fast Backward command.) 0x07 : Pause (ssp1611 stop reading by setting Flag for difUnit interrupt service routine not to read OBrChannel and send MUTE data to difUnit. When Paused ssp1611 need to fade out the audio.) 0x08 : Replay (ssp1611 clears the Flag for difUnit interrupt service routine resume to read the OBrChannel. ssp1611 need to fade in the audio.) 0x09 : Fast Forward 0x0A : Fast Backward 0x0B : Soft Mute (ssp1611 keeps enabling OBrChannel read but discard the data. Send MUTE data to difUnit. Needs to fade out. ) 0x0C : Soft Mute Off 0x0D : FAT Mode2Form2 0x0E : FAT next Dir 0x0F : FAT mp AllOK 0x10 : Compute Total Time 0x11 : Set current decoding time with sector number 0x12 : Repeat start 0x13 : Repeat end 0x14 : Repeat reset 0x15 : Don't use 0x16 : Don't use 0x17 : Don't use 0x18 : FAT joliet NO( read only ISO9660 format ) 0x19 : Display decoding state( No. of song , No. of directory ) 0x1A : Display decoding state( CD format , Total directory ) 0x1B : FAT micom Error 0x1C : FAT micom Exit 0x1d : Don't use 0x1e : Don't use 0x1f : Don't use 0x20 : Don't use 0x21 : Send Header Inform 0x22 : MPEG2 Interpolation On 0x23 : MPEG2 Interpolation Off 0x24 : FAT Check Easy 0x25 : Quick FAT 0x26 : Quick FAT next directory DRAM Interface
47
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
S5L9276 DA0 - 9 DDAT0 - 3 RASB CASB OEB WEB
4Mbit(1M x 4 bit) DRAM 3.3V, 70ns, 1K refresh KM44V1000D (FP) KM44V1004D (EDO) A0 - 9 DQ0 - 3 RAS CAS 1M 1M OE W 1M VDD 1M VDD VDD VDD
Figure 13. Interface with 1Mx4bit DRAM
S5L9276 DA11 DA0 - 10 DDAT0 - 3 RASB CASB OEB WEB
16Mbit(4M x 4 bit) DRAM 3.3V, 60ns, 2K refresh KM44V4100C (FP) KM44V4104C (EDO)
A0 - 10 DQ0 - 3 RAS CAS 1M OE W 1M VDD VDD
Figure 14. Interface with 4Mx4bit DRAM Type (2K ref. product)
48
OPTICAL CD MP3 SYSTEM
S5L9276 (PRELIMINARY SPEC)
S5L9276 DA0 - 11 DDAT0 - 3 RASB CASB OEB WEB
16Mbit(4M x 4 bit) DRAM 3.3V, 60ns, 4K refresh A0 - 11 DQ0 - 3 RAS 1M 1M 1M CAS OE W VDD VDD VDD
Figure 15. Interface with 4Mx4bit DRAM Type B (4K ref. Product)
49
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
NOTES
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